State diagramming environments provide design tools for modeling and simulating event-driven systems and subsystems. State diagrams enable the graphical representation of hierarchical and parallel states and the event driven transitions between them. The state diagrams include both logic and internal data. State diagrams can be used to visually detect a current state during the operation of the system being modeled. An example of a state diagramming environment is Stateflow® from The Math Works, Inc. of Natick, Mass.
A state diagram may be used to represent finite state machines. In hardware design, a circuit with memory constitutes a finite state machine. Finite state machines may be used in the design of sequential circuits, which in general, are circuits that use combinational logic and a memory component. The output and next state of a sequential circuit may be a function of the present state of and/or the input to the sequential circuit. Sequential circuits fall into two categories, asynchronous and synchronous. Asynchronous sequential circuits refer to circuits that do not use a clock to synchronize state transitions. Synchronous sequential circuits refer to sequential circuits that use a clock to synchronize state transitions.
Many hardware designers use a hardware description language, such as VHDL or Verilog, to design sequential circuits. Hardware description languages provide a formal description of a circuit. Unlike high level programming languages, such as C or C++, hardware description languages use syntax and semantics for expressing time and concurrent statements, which are primary attributes of hardware.
For example, an expression of time using a statement in VHDL may be:Clock<=not Clock after 1 ms;This statement creates a periodic signal that has a period of 2 milliseconds. That is, the value of “not Clock” is assigned to “Clock” after every millisecond. So if Clock is initially 0, after 1 millisecond, not Clock is assigned to Clock, where not Clock is 1. Therefore, Clock is now 1, and after another millisecond, not Clock is again assigned to Clock making Clock 0.
An example of concurrent statements using VHDL are:A<=B+C; D<=E+F; The value of A may change any time values B and C change. Likewise the value of D may change any time values E and F change. Further, the order in which the concurrent statements are listed does not affect when they are evaluated. In this manner, hardware description languages are unlike a sequential program that uses a programming language such as C or C++.
A benefit of hardware description languages is that a hardware design using a hardware description language can simulate their design in software before implementing the design in hardware. This ability allows hardware designers to verify their design before implementing the design, and thereby, saves time by reducing the number of iterations needed to implement the design and also provides a cost reduction.
Despite the benefit of hardware description languages, using a hardware description language for hardware design is often complicated and time consuming as compared to using a state diagram. There is a need for the ability to convert a state diagram into a hardware description language suitable for synthesizing and implementing a hardware design. It is also desired that given the ability to convert from a state diagram to a hardware description language that a simulation of the state diagram yield the same result as a simulation of the hardware description language that represents the state diagram.